The present invention relates generally to integrated circuits. More particularly, the present invention relates to apparatus and methods for testing simultaneous bi-directional I/O circuits.
Integrated circuits (ICs) typically contain one or more functional logic blocks (FLB), such as a microprocessor, microcontroller, graphics processor, bus interface circuit, input/output (I/O) circuit, memory circuit, and the like. IC""s are typically assembled into packages that are physically and electrically coupled to a substrate such as a printed circuit board (PCB) or a ceramic substrate to form an xe2x80x9celectronic assemblyxe2x80x9d. The xe2x80x9celectronic assemblyxe2x80x9d can be part of an xe2x80x9celectronic systemxe2x80x9d. An xe2x80x9celectronic systemxe2x80x9d is broadly defined herein as any product comprising an xe2x80x9celectronic assemblyxe2x80x9d. Examples of electronic systems include computers (e.g., desktop, laptop, hand-held, server, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, MP3 (Motion Picture Experts Group, Audio Layer 3) players, etc.), and the like.
In the field of electronic systems there is an incessant competitive pressure among manufacturers to drive the performance of their equipment up while driving down production costs. This is particularly true regarding the testing of ICs, where each new generation of IC""s must provide increased performance while generally being smaller or more compact in size. IC""s must generally be tested before they are incorporated into an electronic assembly in order to verify that each component of each FLB on the IC functions properly and to verify that the input/output (I/O) circuits of each IC operate correctly within specified timing parameters or timing margins.
FIG. 1 illustrates a block diagram of a prior art I/O circuit when outputting data. The I/O circuit comprises a driver circuit 1 and a receiver circuit 2. When the I/O circuit is outputting data, driver circuit 1 is enabled by output enable (OE) signal=1, and driver circuit 1 generates a data-out signal over path 3 to the circuit""s I/O node or pin.
FIG. 2 illustrates a block diagram of a prior art I/O circuit when inputting data. When the I/O circuit is receiving data, driver circuit 1 is disabled by OE=0, and receiver circuit 2 receives a data-in signal over path 4 from the circuit""s I/O node.
In testing IC""s, it is known to employ I/O loopback or switching state (AC) testing, as for example disclosed in Related Inventions Nos. 1 and 2 above. In I/O loopback testing, data is generated by a FLB within the IC and output through the driver or output component of each I/O circuit. Subsequently, the data is received through the receiver or input component of each I/O circuit and conveyed to the FLB to verify that the correct data has been received. In this manner, the IC can verify that the input and output components of each I/O buffer are correctly operating.
FIG. 3 illustrates a block diagram of a prior art I/O circuit operating in a loopback test mode. Driver circuit 1 is enabled by OE=1 and generates data over path 5 that is fed back to the input of receiver 2. Operating the I/O circuit in this manner enables a form of built-in self-test to be performed.
In known prior art I/O loopback testing, the I/O circuit being tested could not operate in native mode (i.e., functioning in the same mode as it would in normal operation). In normal operation, the driver of a conventional I/O circuit is enabled when the I/O circuit is sending data and disabled when the I/O circuit is receiving data. However, in loopback test mode the I/O circuit is forced into a non-native mode of operation, because the driver is enabled while the receiver is receiving. It would be desirable to be able to perform loopback testing on I/O circuits while operating in native mode.
It is known to use simultaneous bi-directional (SBD) I/O circuits in IC""s. For example, U.S. Pat. No. 5,604,450 of Shekhar Borkar et al., which is assigned to the assignee of the present invention, discloses SBD I/O circuits.
FIG. 4 illustrates a block diagram of a prior art simultaneous bi-directional I/O circuit. SBD I/O circuit comprises a driver 6, a differential receiver 7, and a selection circuit 8 such as a multiplexer (MUX). The selection circuit 8 is controlled by the state of the data-out signal (OUT) going into driver 6 and applied via path 10 to a control input of selection logic 8. Two non-zero reference voltages, e.g. xc2xc Vcc and xc2xe Vcc, are applied as inputs to selection logic 8. Selection logic 8 passes a REF voltage level representing one or the other of these reference voltages, depending upon the state of the data-out signal OUT at its control input.
In the SBD form of signaling, the threshold of the differential receiver is adaptively changed between two non-zero reference voltages, e.g. xc2xc Vcc and xc2xe Vcc, depending on whether the data being driven out of the I/O circuit""s I/O node is low or high. Switching the reference level to the receiver in this manner enables the receiver to properly decode the incoming data from the ternary voltage level on the I/O node.
In order to test whether SBD I/O circuits are operating properly, it is desirable to be able to employ a loopback test mode similar to that illustrated in FIG. 3 for non-SBD I/O circuits. However, high-speed operation of an SBD I/O circuit requires precise delay matching between the data path 9 and reference select path 10 to the receiver 7. In addition, high-speed operation also requires that the reference select circuitry switches at a rate that matches the I/O circuit""s output slew rate.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a significant need in the art for an SBD I/O circuit that can be tested in a loopback testing mode that does not disturb the delay-matching or slew-rate matching circuitry of the I/O circuit, and for methods of native-mode testing such I/O circuits on IC""s.